完整後設資料紀錄
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dc.contributor.authorHsieh, Yu-Shengen_US
dc.contributor.authorChang, Yao-Jenen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.date.accessioned2017-04-21T06:49:13Z-
dc.date.available2017-04-21T06:49:13Z-
dc.date.issued2015en_US
dc.identifier.issn0569-5503en_US
dc.identifier.urihttp://hdl.handle.net/11536/135774-
dc.description.abstractA high yielding fine-pitch submicron Cu/Sn bonding scheme has been successfully demonstrated. With inserting the ultra-thin buffer layer, near sub-micron thickness Cu/Sn pad bonding can be achieved. The fine pitch Cu/Sn interconnects can be also further extended. The modified Kelvin feature in chip level and tens of thousands series interconnects per chip with a density of 3.4 x 10(5)/cm(2) in wafer level are fabricated and completely investigated on electrical characteristics. Several critical reliability assessments, such as TCT and unbias HAST, are also investigated the variation and standard error of the fine-pitch pad bonding scheme. With excellent mechanical properties, bonding quality, electrical and reliability results, the approach is suitable for future 3D vertical interconnects.en_US
dc.language.isoen_USen_US
dc.titleDevelopment and Electrical Investigation of Novel Fine-Pitch Cu/Sn Pad Bumping Using Ultra-Thin Buffer Layer Technique in 3D Integrationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC)en_US
dc.citation.spage591en_US
dc.citation.epage596en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000370285100090en_US
dc.citation.woscount1en_US
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