Title: | Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology |
Authors: | Lee, Yao-Jen Hou, Fu-Ju Chuang, Shang-Shiun Hsueh, Fu-Kuo Kao, Kuo-Hsing Sung, Po-Jung Yuan, Wei-You Yao, Jay-Yi Lu, Yu-Chi Lin, Kun-Lin Wu, Chien-Ting Chen, Hisu-Chih Chen, Bo-Yuan Huang, Guo-Wei Chen, Henry J. H. Li, Jiun-Yun Li, Yiming Samukawa, Seiji Chao, Tien-Sheng Tseng, Tseung-Yuen Wu, Wen-Fa Hou, Tuo-Hung Yeh, Wen-Kuan 電子物理學系 電機學院 電子工程學系及電子研究所 Department of Electrophysics College of Electrical and Computer Engineering Department of Electronics Engineering and Institute of Electronics |
Issue Date: | 2015 |
Abstract: | We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl-2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I-on/I-off ratio exceeding 10(8), the highest ever reported for Ge-based pFETs. |
URI: | http://hdl.handle.net/11536/136038 |
ISBN: | 978-1-4673-9894-7 |
Journal: | 2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) |
Appears in Collections: | Conferences Paper |