完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tang, Kai-Neng | en_US |
dc.contributor.author | Liao, Seian-Feng | en_US |
dc.contributor.author | Ker, Ming-Dou | en_US |
dc.contributor.author | Chiou, Hwa-Chyi | en_US |
dc.contributor.author | Huang, Yeh-Jen | en_US |
dc.contributor.author | Tsai, Chun-Chien | en_US |
dc.contributor.author | Jou, Yeh-Ning | en_US |
dc.contributor.author | Lin, Geeng-Lih | en_US |
dc.date.accessioned | 2017-04-21T06:49:29Z | - |
dc.date.available | 2017-04-21T06:49:29Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4799-6670-7 | en_US |
dc.identifier.issn | 2162-7673 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/136217 | - |
dc.description.abstract | Electrostatic discharge (ESD) and latchup are important reliability issues to the CMOS integrated circuits in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS has been verified to sustain a high ESD level with high holding voltage in a 0.25-mu m BCD process. Stacked devices in different configuration were also investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2015 ASIA-PACIFIC SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC) | en_US |
dc.citation.spage | 325 | en_US |
dc.citation.epage | 328 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000380499800048 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |