Scalable Mutli-Layer Barrier Synchronization on NoC

Abstract

Barrier is a widely used synchronization mechanism adopted in different scales of parallel systems. Being a global operation in a system, scalability has become a critical design concern of the barrier implementation. Reducing the number of messages and hop count are main challenges for attaining a well-scalable barrier design. This paper proposes an efficient control mechanism and communication scheme for barrier operations and exploits novel multi-layer barrier algorithms on NoC (Network on Chip) based multiprocessor systems. A novel barrier controller and communication unit are introduced to enable efficient barrier synchronization on NoC. The proposed modules improve the cooperative communication between synchronization messages, and can be easily integrated into a general NoC switch. For a 32x32 network, the proposed 2-layer barrier can respectively reduce the latency and hop count up to 61.7% and 99.3%. The experimental results have also revealed in-depth analysis of different design options.