標題: True 50% Duty-Cycle High-Speed Divider with the Modulus of Odd Numbers
作者: Tseng, Sheng-Che
Wei, Hung-Ju
Syu, Jin-Siang
Meng, Chinchun
Tsung, Kuan-Chang
Huang, Guo-Wei
電信工程研究所
Institute of Communications Engineering
關鍵字: 50% duty cycle;divide-by-N;prescaler;SiGe HBT
公開日期: 2009
摘要: This paper proposes a true 50% duty-cycle highspeed prescaler with an odd modulus, based on current switchable D flip-flops. Each D flip-flop can sample data at the positive and negative clock edges, because of the changeable trigger mode. The proposed divide-by-N prescaler, with a 50% duty cycle, is formed as a ring with an N number of D flip-flops. Two types of 50% duty-cycle divide-by-five prescalers, the sample-hold-sample-hold-hold (SHSHH) prescaler and the sample-sample-hold-sample-hold (SSHSH) prescaler, are implemented using the 0.35 mu m SiGe HBT technology. The SHSHH divider has a better performance, up to 7 GHz, thanks to the synchronization of data and control signals.
URI: http://hdl.handle.net/11536/13767
ISBN: 978-1-4244-2801-4
期刊: APMC: 2009 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5
起始頁: 305
結束頁: 308
Appears in Collections:Conferences Paper