適用於極低電壓之超大型積體電路設計的一種新型現場錯誤偵測及錯誤修正技術

Abstract

隨著生醫電子與穿戴是裝置的興起，這些以電池作為能量來源的產品，因為產品本身大小的限制，使得這些裝置能使用的電池容量都相當有限，而要如何有效率的使用這有限的能源也變成一個相當重要的課題。電壓調節(voltage scaling)是一種透過調降工作電壓而能有效降低功率與能量消耗的一種技術，而透過將工作電壓調降至近臨界電壓或甚至到次臨界電壓可以得到最小能量消耗點(minimum energy point)。這告訴了我們，若是希望有更好的能源效率(energy efficiency)，那就應該讓電路操作在近臨界電壓甚至之下。可是要讓電路操作在這麼低的電壓是相當困難的，因為在低電壓時，延遲變異(delay variation)會變得非常大，而這在傳統的最差情況設計中會造成很大的負擔，也就是為了保護少部分最差情況的晶片，而讓大部分的晶片付出龐大的面積與功率的負擔。為了解決這一問題，就有人提出了優於最差情況設計(Better than worst-case design)，主要的概念是應該針對大部分的情況去做最佳化，當少部分的最差情況發生時，再想辦法補救，即是在設計時暫時不考慮最差情況而以較寬鬆的時間條件來設計，而當最差情況發生時，再以錯誤偵測電路來偵測設定時間錯誤。為此則需要一個有效率，低負擔的錯誤偵測與錯誤修正技術。我們提出的錯誤偵測與錯誤修正技術利用毛刺偵測的方式來判斷訊號是否已經穩定，也就是電路是否已經完成運算，當偵測到來不及完成運算，即是設定時間錯誤發生時就利用時脈閘控立即暫停一個週期來讓電路完成運算。我們在40奈米的製程下實現了一個感測器平台，並在其中簡化指令集處理器(RISC)實現了提出的錯誤偵測與錯誤修正技術，並只有0.36%面積負擔。經量測相比於傳統的最差情況設計，可以有46%的能量節省，或是在相同能量消耗下可以提升116/%的吞吐量。

With the increasing demand of biomedical electronic and wearable devices, low power is no longer the only consideration. Due to the small size of these product, the battery capacity is very limited, and therefore, how to use these energy efficiently is the most important considerations to design. Voltage scaling is an efficient technique to reduce power and energy consumption by scaling down the operating voltage. And when the operating voltage scaling down to near/sub-threshold voltage, there has a minimum energy consumption point. It means that if we want better energy efficiency, than we should let the circuit operate at near/sub-threshold voltage. However, design circuit for near-threshold voltage operation is challenging. The circuit operate under near-threshold voltage increase not only the circuit delay but also the delay variation. Unfortunately, conventional worst-case design in order to guarantee the chips are always correct in any corner, will sizing the circuit in large size and cause significantly area and power overhead. To solve this problem, the better-than-worst-case (BTWC) design technique was presented. Main idea of BTWC is design and optimize for common case and ignore worst-case in design time, so that the BTWC use the relaxed timing constrain to analyze and synthesize the design. When the worst-case happen in run time, the setup timing error will occur and need the setup timing error detection and correction. Therefore we need a efficiency and low area overhead error detection and correction. The proposed error detection and correction technique use the glitch detection to determine setup timing error by detect the signal is stable or not. When the error was detected, the correction will be trigger and gating clock immediately to give circuit one more cycle to finish computation. In order to verify purposed techniques, we implement a sensing platform and realize the proposed technique in the RISC processor at 40nm process. The proposed techniques has 0.36% area overhead of total area. And the proposed techniques has 46% energy saving or 116% throughput improve at same energy consumption compare with conventional worst-case design.