應用於低功率消耗操作且具製程、電壓、溫度變 異補償技術之近臨界電壓全數位鎖相迴路

Abstract

由於在動態電壓頻率調整與低功率消耗應用操作中，需要快速的頻率轉換，擁有快速鎖定特性及低功率消耗的時脈產生器是必要的，進而產生不同頻率的時脈訊號。數位邏輯天生上能夠在高雜訊環境中正常操作，甚至可在超低系統電壓下操作。因此，對雜訊具高免疫性的全數位鎖相迴路就適合應用在系統單晶片整合上。其中，數位控制振盪器是全數位鎖相迴路電路最重要的模組單元，其也決定全鎖位鎖相迴路的鎖定頻率範圍與抖動特性。除此之外，數位控制振盪器的功率消耗也無法被忽略。另外，在全數位鎖相迴路操作上，參考突波則會因為週期性地改變數位控制振盪器的數位控制碼而產生。嚴重的參考突波會混合周遭通道訊號而衰減傳輸端與接收端性能。因此，在進行全數位鎖相迴路電路設計時，其快速鎖定時間(大的迴路頻寬) 與在頻寬內參考突波大小參數決定時，其特性折衷與取捨就是一個重要課題。 提出一可於GP-65 奈米互補式金屬氧化半導體製程技術下實現出一具階層閘式、多頻帶數位控制振盪器且近臨界操作性能之全數位鎖相迴路, 其符合低電壓規格應用。首先，針對於總體的、局部的製程變異及溫度變異在閘極式數位控制振盪器影響程度, 已透過模擬與分析以評估其變異情況對於65 奈米互補式金屬氧化半導體製程技術實現且 操作於近臨界電壓數位控制振盪器電路特性影響。除此之外，閘極數位控制振盪器具高線性度特性以符合低抖動特性性能。第二，提出一可應用於頻率追鎖的新式時域階層頻率估計演算法, 且其振盪器輸出頻率可於1.5 參考時間週期決定。這快速鎖定時間將適用於動態電壓頻率調整系統或是事件觸發驅動應用。 提出一可於GP-40 奈米互補式金屬氧化半導體製程技術下實現出具多相位差動輸出之電壓控制電容式數位控制振盪器，其可應用於低功率消耗系統。呈現一新式數位控制振盪器，其電容負載使用N 通道金屬氧化半導體，可展現出高解析度特性與頻率線性度，因而改善數位控制振盪器的抖動特性。此外，具多頻帶技術，所提數位控制振盪器能可達到低功率消耗且面積僅具1656 平方微米。當操作在0.55 伏特電壓下，當數位控制振盪器操作於16.4 億赫茲輸出頻率下，其功率消耗為0.28 毫瓦特且具1.99 皮秒(百分之0.33 單位間隔) 抖動特性。因此，在高速輸出頻率操作下，每單位週期能量為0.17 (皮焦耳) 且低於百分之0.5 的抖動性能使所提數位控制振盪器適合操作於低能 量且高速時脈應用。可在LP-65 奈米互補式金屬氧化半導體製程呈現具多相位且單調特性數位控制振盪器之全數位鎖相迴路，其可應用於近臨界電壓操作且適用於低供應電壓應用。除此之外，一利用多相位隨機取樣技術來有效展開參考時脈頻率之新全數位參考突波抑制電 路被提出來改善頻譜特性且同時保持低抖動性能。因為等效參考時脈頻率被保持，所以整體迴路行為並沒有改變。所提的突波抑制電路面積僅佔全數位鎖相迴路的百分之4.9 (0.038 平方釐米)。當啟動突波抑制電路時，所提全數位鎖相迴路參考突波在100 百萬赫茲輸出頻率改善至-57.3 分貝，除此之外，其週期抖動為百分之0.217 單位間隔。因此，在100 百萬赫茲輸出頻率, 其5.1 分貝改善的參考突波與低於百分之0.3 單位間隔性能，能夠使所提全數位鎖相迴路適用於低抖動且低突波應用。 首先，提出可在LP-65 奈米互補式金屬氧化半導體製程實現，且具功率管理單元之全數位鎖相迴路，其可應用於近臨界電壓操作且適用於低供應電壓應用。具功率管理單元之全數位鎖相迴路，能夠可靠地在不同變異環境中正常操作，且同時降低功率消耗。除此之外，所提全數位鎖相迴路在130 百萬赫茲輸出頻率下，其功率消耗減少了百分之39，且其降電壓轉換器功率消耗僅為30 微瓦特。再者，也提出可在GP-65 奈米互補式金屬氧化半導體製程實現，且具功率管理單元之全數位鎖相迴路，其可針對製程、電壓、溫度變異進行補償。其內含的溫度偵測器與製程、溫度條件查找表設計，也可用來協助進行製程、電壓、溫度變異補償。所提全數位鎖相迴路在100 百萬赫茲輸出頻率下，其功率消耗在0.5/0.42 伏特供應電壓操作下，為211/131 微瓦特，在百分之16 的供應電壓下降下，其功率消耗也減少了百分之38。因此，具高轉換效率功率管理單元之全數位鎖相迴路適合在事件驅動與低電壓操作應用。 -

Due to the demand of fast frequency conversion during the dynamic voltage frequency scaling (DVFS) operation and low power applications, a clock generator with fast lock-in performance and low power consumption is mandatory to provide different frequencies. Digital logic can be operated in the noisy environment or even at a ultra-low supply voltage. As a result, all-digital phase-locked loops (ADPLLs) with the innate high-immunity to noise are favorable for system-on-chip (SoC) integration. Digitally controlled oscillators (DCOs), which are the most critical components in ADPLLs, determine the lock-in range and jitter performance of ADPLLs. Moreover, a DCO contributes the power consumption which cannot be neglected in an ADPLL design. The serious reference spurs of ADPLLs are generated by the periodic updating on the digital control word of the DCO. Large reference spurs will mix the signals from adjacent channels to degrade both transmitter and receiver performance. The design trade-off in an ADPLL between fast lock-in time (large loop bandwidth) and the magnitude of in-band reference spurs is a critical issue. An ADPLL with a hierarchical multi-band G-DCO and the near-threshold operation capability is proposed in GP-65 nm CMOS process and is suitable to the low supply voltage applications. Firstly, the simulation and analysis of G-DCO with global, local process and temperature variations is carried out to evaluate the variation impact on circuit performance when operating at a near-threshold supply voltage in 65 nm CMOS process. Moreover, the high linearity of G-DCO is guaranteed to acquire the low jitter performance. Secondly, a new time-domain hierarchical frequency estimation algorithm (HFEA) for frequency acquisition is proposed in this work to determine the output frequency in 1.5 reference clock cycles. The proposed ADPLL is suitable to the DVFS systems or event-driven applications. A varactor-based DCO with multi-phase differential outputs is proposed in GP-40 nm CMOS process for low-power applications. A new DCO with NMOS varactors as capacitive loading cells is proposed to acquire high resolution and high linearity characteristic. The DCO jitter performance is further improved. Moreover, the low power consumption and low area of 1656 m2 can be acquired with multi-band techniques. When operated in 0.55 V VDD, the power consumption is 0.28 mW at 1.64 GHz with a jitter performance of 1.99 ps (0.33% UI). Consequently, the jitter performance below 0.5% UI and 0.17 (pJ) energy consumption per cycle at high-speed clock frequency make the proposed DCO suitable in low-energy and high-speed applications. A near-threshold operation ADPLL with a multi-phase and monotonic capability DCO is proposed in LP-65 nm CMOS process and is suitable to the low supply voltage applications. A new all-digital reference spur suppression (RSS) circuit with random-sampling techniques to effectively spread the reference clock frequency is proposed to improve the spectrum performance and the low-jitter performance is preserved as well. As a result of using the same equivalent reference clock frequency for spur suppression,the same loop behavior is maintained. The area of reference spur suppression is only 4.9% of the proposed ADPLL with 0.038 mm2. When the spur suppression circuit is activated, the reference spur of -57.3 dBc at 100 MHz output clock frequency is measured with the rms period jitter of 21.7 ps (0.217%). Consequently, the reference spur improvement of 5.1 dBc and the low jitter performance below 0.3% UI at 100 MHz output clock frequency make the proposed ADPLL suitable in low-jitter and low-spur applications. First, a near-threshold ADPLL with a PMU is proposed in LP-65 nm CMOS process for low supply voltage applications. With the PMU, the proposed ADPLL can work well over variations and the ADPLL power consumption is reduced as well. With the PMU, the ADPLL power consumption at 130 MHz output frequency is improved to be 39% when the measured BC power consumption is 30 W. Second, a ADPLL with PMU design is proposed in GP-65 nm CMOS process for PVT compensation. Temperature sensor (TS) and the process and temperature condition look-up table designs are combined for PVT compensation. The ADPLL dissipates 211/131 W at 100 MHz under 0.5/0.42 V VDD. About 38% power reduction is achieved by 16% lowering in voltage. As a result, those properties make the proposed ADPLL with high efficiency PMU favourable to eventdriven or low-voltage applications.