應用TRIZ方法與實驗設計進行半導體製程改善

Abstract

在半導體金屬導體連線技術，會利用蝕刻製程(etch)將金屬介電層(inter-metal dielectric，IMD)形成孔洞(via holes)後，填入金屬以形成連結每層平面金屬導電線路的垂直金屬插栓(plugs)，這種金屬層與金屬層之間的連接導通，也稱為介層插栓（via plugs）。常見的介電層孔洞製程是蝕刻單一類薄膜層，這層絕緣隔離的介電層薄膜通常為二氧化矽(SiO2)；在蝕刻過程中產生的高分子會被接下來的洗淨製程去除以利後續金屬填洞。而本論文要探討的是：針對客製化製程中之介電層鑲嵌氮化矽(Si3N4)薄膜的孔洞製作過程易產生難以清除的高分子殘留進行改善。 本研究應用TRIZ常見的幾個工具/方法，並遵循其建議步驟，推論得到45個可能的改善方法，最後再整合為34個。考量現行工廠可提供之資源，本文提出5個因子先執行25-2部分因子實驗，篩選出了2個顯著因子(A：HF洗淨和C：氮化矽蝕刻O2沖洗)，且解釋能力足夠(R2=85.77%>80%)。然而此設計之解析度只有III，故主效應和2因子交互作用相互交絡。然因實際資料在交互作用圖上有觀察到交互作用項(AE，E：灰化製程溫度)，乃將2個主效應因子(A,C)和相關的交互作用因子(E)執行23全因子之驗證實驗；實驗結果發現只有C因子顯著，而且沒有顯著的交互作用項，故最後提出了鑲嵌氮化矽薄膜蝕刻時加入O2沖洗方式來改善。

It is usual in semiconductor manufacturing process to perform a via-hole process in the inter-metal dielectric layer (IMD), and then filled in metal to form a vertical metal plug (also known as “Via Plug” ) to connect two metal layers on different planes. The common via-hole process is to etch a single and simple dielectric film, which is usually silicon dioxide (SiO2), as the insulating layer. The polymer produced during the etch process needs to be removed by the cleaning process in order to have good metal fillings in holes. In this thesis, we discuss how to reduce polymer residue when making via-holes of multi-dielectric films, SiO2-Si3N4-SiO2. In this study, 5 factors were chosen from 34 potential improvement ideas created by applying the TRIZ method due to limited resources. Subsequently, we conducted a 25-2 partial factorial experiment, resulting 2 significant factors, HF clean and Si3N4 etch with O2 flush, with R2=85.77%>80%. Because the 25-2 partial factorial design is a resolution III design, the main effects and 2-factor interactions are confounded and certain 2-factor interaction appears in the interaction plots. As a validation experiment, a 23 full factorial experiment are conducted. With the result of experiment, we propose applying Si3N4 etching with O2 flush to reduce the amount of polymer residue.