標題: Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse
作者: Chang, Chih-Cheng
Chen, Pin-Chun
Chou, Teyuh
Wang, I-Ting
Hudec, Boris
Chang, Che-Chia
Tsai, Chia-Ming
Chang, Tian-Sheuan
Hou, Tuo-Hung
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Neuromorphic computing;RRAM;synapse;multilayer perceptron
公開日期: 1-Mar-2018
摘要: Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses, because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit data set to 87.8%/94.8% by using 6-/8-b analog synapses, respectively, with extremely high asymmetric nonlinearity.
URI: http://dx.doi.org/10.1109/JETCAS.2017.2771529
http://hdl.handle.net/11536/144798
ISSN: 2156-3357
DOI: 10.1109/JETCAS.2017.2771529
期刊: IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
Volume: 8
起始頁: 116
結束頁: 124
Appears in Collections:Articles