標題: | DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers |
作者: | Chen, Zuow-Zun Kuan, Yen-Cheng Li, Yilei Hu, Boyu Wong, Chien-Heng Chang, Mau-Chung Frank 交大名義發表 國際半導體學院 National Chiao Tung University International College of Semiconductor Technology |
關鍵字: | Digital phase-locked loop (DPLL);frequency synthesizer;phase noise cancellation;radio receiver;ring oscillator (RO);sub-sampling time-to-digital converter (TDC) |
公開日期: | 1-四月-2017 |
摘要: | In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. A receiver prototype is fabricated in standard 65-nm CMOS technology. It demonstrates a phase noise reduction from -88 to -109 dBc/Hz at 1-MHz offset and an integrated phase noise reduction from -16.8 to -34.6 dBc when operating at 2.4 GHz. |
URI: | http://dx.doi.org/10.1109/JSSC.2017.2647925 http://hdl.handle.net/11536/145344 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2017.2647925 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 52 |
起始頁: | 1134 |
結束頁: | 1143 |
顯示於類別: | 期刊論文 |