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dc.contributor.authorYou, Wei-Xiangen_US
dc.contributor.authorSu, Pinen_US
dc.date.accessioned2018-08-21T05:54:20Z-
dc.date.available2018-08-21T05:54:20Z-
dc.date.issued2017-08-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2017.2714687en_US
dc.identifier.urihttp://hdl.handle.net/11536/145831-
dc.description.abstractWith the aid of an analytical and scalable model, this paper explores the design space for negative-capacitance (NC) field-effect transistors (FETs) with a 2D semiconducting transition-metal-dichalcogenide channel. In addition, the impact of back-gate biasing on the design space and the body effect of 2D-NCFETs is also investigated. Our study indicates that, to mitigate the conflict between subthreshold swing and hysteresis and to maximize the design space for the 2D-NCFET, a thin buried oxide and an adequate reverse back-gatebias can be applied to achieve the optimum design.en_US
dc.language.isoen_USen_US
dc.subject2D semiconductorsen_US
dc.subjectback-gate biasingen_US
dc.subjectferroelectric FETen_US
dc.subjectLandau-Khalatnikov (L-K) equationen_US
dc.subjectmolybdenum disulphide (MoS2)en_US
dc.subjectnegative-capacitance field-effect transistor (NCFET)en_US
dc.subjecttransition-metal-dichalcogenide (TMD)en_US
dc.titleDesign Space Exploration Considering Back-Gate Biasing Effects for 2D Negative-Capacitance Field-Effect Transistorsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2017.2714687en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume64en_US
dc.citation.spage3476en_US
dc.citation.epage3481en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000406268900063en_US
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