標題: 28nm Near/Sub-Threshold Dual-Port FIFO Memory for Shared Queues in Multi-Sensor Applications
作者: Wu, Yi-Chun
Huang, Po-Tsang
Wu, Shang-Lin
Lung, Sheng-Chi
Wang, Wei-Chang
Hwang, Wei
Chuang, Ching-Te
電子工程學系及電子研究所
國際半導體學院
Department of Electronics Engineering and Institute of Electronics
International College of Semiconductor Technology
公開日期: 1-Jan-2018
摘要: For an energy-limited multi-sensing platform, ultra-low-power queueing design is one of the critical challenge to store low-speed sensing data with various sampling frequencies. In this paper, a near/sub-threshold dual-port first-in-first-out (FIFO) memory is proposed for shared queues in a unified queuing architecture. This ultra-lowpower FIFO memory is designed and implemented using bitinterleaved 12T near-/sub-threshold dual-port SRAM bit-cells, write/read-assist circuitries, and adaptive timing tracking circuits. The 12T bit-cell eliminates both read and write half-select disturbance. Additionally, an adaptive timing tracing circuitry and negative bit-line circuits are employed to against PVT variation and to enhance write ability, respectively. Furthermore, the self-timed pointers and short ripple bit-lines are designed to avoid global long metal lines with large loading. A 256x16 dual-port FIFO memory is implemented in UMC 28nm HKMG CMOS technology. This FIFO memory can be operated at 0.4V with 10MHz for read operations. Moreover, up to 60% power reduction can be achieved based on the proposed design techniques.
URI: http://hdl.handle.net/11536/150806
ISSN: 2474-2724
期刊: 2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)
Appears in Collections:Conferences Paper