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dc.contributor.authorTseng, Tien-Hungen_US
dc.contributor.authorLi, Shou-Chunen_US
dc.contributor.authorWu, Kai-Chiangen_US
dc.date.accessioned2019-04-02T06:04:32Z-
dc.date.available2019-04-02T06:04:32Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn1081-7735en_US
dc.identifier.urihttp://dx.doi.org/10.1109/ATS.2018.00025en_US
dc.identifier.urihttp://hdl.handle.net/11536/151041-
dc.description.abstractDue to escalating complexity of hardware design and manufacturing, integrated circuits (ICs) are designed and fabricated in multiple nations, so are software tools. It makes hardware security become more subject to various kinds of tampering in the supply chain. Hardware Trojan horses (HTHs) can be implanted to facilitate the leakage of confidential information or cause the failure of a system. Reliability Trojan is one of the main categories of HTH attacks because its behavior is progressive and thus hard to be detected, or not considered malicious. In this work, we propose to insert reliability Trojan into a circuit which can finely control the circuit lifetime as specified by attackers (or even designers), based on manipulating BTI-induced aging behavior in a statistical manner, with the consideration of process variations (PVs). Experimental results show that, given a specified lifetime target and under the influence of PVs, the circuit is highly likely to fail within a desired lifetime interval, at the cost of little area overhead.en_US
dc.language.isoen_USen_US
dc.subjectlifetime Trojanen_US
dc.subjectduty cycleen_US
dc.subjectagingen_US
dc.subjecttiming violationen_US
dc.titleLifetime Reliability Trojan based on Exploring Malicious Agingen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ATS.2018.00025en_US
dc.identifier.journal2018 IEEE 27TH ASIAN TEST SYMPOSIUM (ATS)en_US
dc.citation.spage74en_US
dc.citation.epage79en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000458678300014en_US
dc.citation.woscount0en_US
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