Using power gating techniques in area-array SoC floorplan design

Abstract

Low power demand drives the development of lower power design architectures, among which power gating is one of the state-of-the-art techniques to achieve low power. NITCMOS (or sleep transistor) is applied when some of the blocks can be switched off without leakage power dissipation. This technique is widely used in circuit level design, but hardly used in higher level design stage. Due to early planning in power delivery for area-array design style, it is necessary to consider the power gating techniques in early SoC physical design stage. This paper presents a framework to insert coarse grain MTCMOS in SoC floorplanning stage, saving mainly leakage power. This work decides which modules have chance to save power by sleep transistors insertion, and reserves enough area for them during floorplarming. The results show that our approach works well and can obtain lower power floorplans with supply noise aware sleep transistor insertion in area-array architecture.