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dc.contributor.authorChun-Yen Changen_US
dc.date.accessioned2019-04-11T05:48:20Z-
dc.date.available2019-04-11T05:48:20Z-
dc.date.issued2017-11-02en_US
dc.identifier.govdocH01L051/05en_US
dc.identifier.govdocH01L051/10en_US
dc.identifier.govdocH01L027/28en_US
dc.identifier.govdocH01L051/00en_US
dc.identifier.urihttp://hdl.handle.net/11536/151309-
dc.description.abstractA field effect transistor (FET) structure includes a substrate, an internal gate, an insulation layer, a semiconductor strip, a gate dielectric insulator, and a gate conductor. The internal gate includes a floor portion located on the substrate and a wall portion extending from the floor portion. The insulation layer is located on the floor portion of the internal gate. The semiconductor strip is located on the wall portion and a portion of the insulation layer, and the semiconductor strip includes source/drain regions and a channel region adjacent to the source/drain regions. The gate dielectric insulator is located on the channel region. The gate conductor is located on the gate dielectric insulator.en_US
dc.language.isoen_USen_US
dc.titleFIELD EFFECT TRANSISTOR STRUCTUREen_US
dc.typePatentsen_US
dc.citation.patentcountryUSAen_US
dc.citation.patentnumber20170317302en_US
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