完整後設資料紀錄
DC 欄位語言
dc.contributor.authorHuang, Ya-Shihen_US
dc.contributor.authorLiu, Yang-Hsiangen_US
dc.contributor.authorHuang, Juinn-Daren_US
dc.date.accessioned2014-12-08T15:21:19Z-
dc.date.available2014-12-08T15:21:19Z-
dc.date.issued2011en_US
dc.identifier.isbn978-0-7695-4447-2en_US
dc.identifier.issn2159-3477en_US
dc.identifier.urihttp://hdl.handle.net/11536/15131-
dc.identifier.urihttp://dx.doi.org/10.1109/ISVLSI.2011.16en_US
dc.description.abstractThree-dimensional (3D) design technology, which has potential to significantly improve design performance and ease heterogeneous system integration, has been extensively discussed in recent years. This emerging technology allows stacking multiple layers of dies and typically resolves the vertical inter-layer connection issue by through-silicon vias (TSVs). However, TSVs also occupy significant silicon estate as well as incur reliability problems. Therefore, the deployment of TSVs must be very judicious in 3D designs. In this paper, we propose an iterative layer-aware partitioning algorithm, named iLap, for TSV minimization in 3D structures. iLap iteratively applies multi-way min-cut partitioning to gradually divide a given design layer by layer in the bottom-up fashion. Meanwhile, iLap also properly fulfills a specific I/O pad constraint incurred by 3D structures to further improve its outcome. Experimental results show that iLap can reduce the number of TSVs by about 35% as compared to several existing state-of-the-art methods. We believe a good TSV-minimized 3D partitioning solution can serve as a good starting point for further tradeoff operations between TSV count and wirelength.en_US
dc.language.isoen_USen_US
dc.subjectthrough-silicon via (TSV)en_US
dc.subject3D integration technologyen_US
dc.subjectlayeringen_US
dc.subjectpartitioningen_US
dc.titleLayer-Aware Design Partitioning for Vertical Interconnect Minimizationen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ISVLSI.2011.16en_US
dc.identifier.journal2011 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI)en_US
dc.citation.spage144en_US
dc.citation.epage149en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000298386100025-
顯示於類別:會議論文


文件中的檔案:

  1. 000298386100025.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。