Device Structural Effects on Negative-Capacitance FETs

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Su, Pin	en_US
dc.contributor.author	You, Wei-Xiang	en_US
dc.date.accessioned	2019-05-02T00:26:47Z	-
dc.date.available	2019-05-02T00:26:47Z	-
dc.date.issued	2018-01-01	en_US
dc.identifier.isbn	978-1-5386-7627-1	en_US
dc.identifier.issn	2573-5926	en_US
dc.identifier.uri	http://hdl.handle.net/11536/151720	-
dc.description.abstract	This paper discusses several device structural effects on negative-capacitance FETs (NCFETs) with emphasis on the wide-range average subthreshold swing. We point out and explain the intrinsic difference between SOI and double-gate 2D NCFETs. The impact of drain coupling on the NC effect and its implication on the design of short-channel NC-FinFETs are also addressed.	en_US
dc.language.iso	en_US	en_US
dc.title	Device Structural Effects on Negative-Capacitance FETs	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2018 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S)	en_US
dc.citation.spage	0	en_US
dc.citation.epage	0	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000462960700047	en_US
dc.citation.woscount	0	en_US
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