標題: A 1-V 175-mu W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques
作者: Liao, Sheng-Hui
Wu, Jieh-Tsorng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Analog-digital conversion;delta-sigma modulator (DSM);multistage noise-shaping (MASH);switched-capacitor (SC) circuit
公開日期: 1-Sep-2019
摘要: A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 mu W from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is 1.13 x 0.34 mm(2).
URI: http://dx.doi.org/10.1109/JSSC.2019.2925273
http://hdl.handle.net/11536/152825
ISSN: 0018-9200
DOI: 10.1109/JSSC.2019.2925273
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 54
Issue: 9
起始頁: 2523
結束頁: 2531
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