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dc.contributor.authorWu, Tse-Weien_US
dc.contributor.authorLee, Dong-Zhenen_US
dc.contributor.authorWu, Kai-Chiangen_US
dc.contributor.authorHuang, Yu-Haoen_US
dc.contributor.authorChen, Ying-Yenen_US
dc.contributor.authorChen, Po-Linen_US
dc.contributor.authorChern, Masonen_US
dc.contributor.authorLee, Jih-Nungen_US
dc.contributor.authorKao, Shu-Yien_US
dc.contributor.authorChao, Mango C. -T.en_US
dc.date.accessioned2019-10-05T00:09:48Z-
dc.date.available2019-10-05T00:09:48Z-
dc.date.issued2019-01-01en_US
dc.identifier.isbn978-1-7281-1170-4en_US
dc.identifier.issn1093-0167en_US
dc.identifier.urihttp://hdl.handle.net/11536/152981-
dc.description.abstractConventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) or between two cells (dual-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell and dual-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. However, it was considered computationally infeasible to simulate every possible defective scenario for a cell library and obtain a complete set of cell-level fault models. In this paper, we present a new dual-cell-aware (DCA) framework based on examining the layout of two adjacent cells (i.e., a dual cell) to identify potential defects, where time-consuming RC extraction can be avoided and the runtime for SPICE simulation can be reduced. Experimental results and silicon data on a SoC product show that the proposed DCA framework can not only save runtime significantly but also maintain the promising efficacy of DCA tests for the objective of lowering DPPM.en_US
dc.language.isoen_USen_US
dc.titleLayout-Based Dual-Cell-Aware Testsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2019 IEEE 37TH VLSI TEST SYMPOSIUM (VTS)en_US
dc.citation.spage0en_US
dc.citation.epage0en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000485799500030en_US
dc.citation.woscount0en_US
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