標題: High-Performance Charge-Trapping Flash Memory Device With an Ultrathin 2.5-nm Equivalent-Si(3)N(4)-Thickness Trapping Layer
作者: Tsai, C. Y.
Chin, Albert
電機工程學系
Department of Electrical and Computer Engineering
公開日期: 1-Jan-2012
摘要: We made the MoN-[SiO(2)-LaAlO(3)]-[Ge-HfON]-[LaAlO(3)-SiO(2)]-Si charge-trapping (CT) Flash device with a record-thinnest 2.5-nm equivalent-Si(3)N(4)-thickness trapping layer, a large 4.4-V initial memory window, a 3.2-V ten-year extrapolated retention window at 125 degrees C, and a 3.6-V endurance window at 106 cycles, under very fast 100 mu s and low +/- 16-V program/erase pulses. These were achieved using Ge reaction with a HfON trapping layer for better CT and retention.
URI: http://dx.doi.org/10.1109/TED.2011.2171970
http://hdl.handle.net/11536/15329
ISSN: 0018-9383
DOI: 10.1109/TED.2011.2171970
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 59
Issue: 1
起始頁: 252
結束頁: 254
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