完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wang, X. Shawn | en_US |
dc.contributor.author | Chan, Chi-Hang | en_US |
dc.contributor.author | Du, Jieqiong | en_US |
dc.contributor.author | Wong, Chien-Heng | en_US |
dc.contributor.author | Li, Yilei | en_US |
dc.contributor.author | Du, Yuan | en_US |
dc.contributor.author | Kuan, Yen-Cheng | en_US |
dc.contributor.author | Hu, Boyu | en_US |
dc.contributor.author | Chang, Mau-Chung Frank | en_US |
dc.date.accessioned | 2020-01-02T00:03:29Z | - |
dc.date.available | 2020-01-02T00:03:29Z | - |
dc.date.issued | 2018-01-01 | en_US |
dc.identifier.isbn | 978-1-5386-4545-1 | en_US |
dc.identifier.issn | 1529-2517 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/153335 | - |
dc.description.abstract | This paper presents an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. A two-level 2x8 master-slave hierarchical interleaved architecture is employed. A complementary dual-loop-assisted buffer is proposed to achieve both high linearity and bandwidth with low power. This time-interleaved ADC achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers. | en_US |
dc.language.iso | en_US | en_US |
dc.title | An 8.8-GS/s 8b Time-Interleaved SAR ADC with 50-dB SFDR Using Complementary Dual-Loop-Assisted Buffers in 28nm CMOS | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE 2018 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC) | en_US |
dc.citation.spage | 88 | en_US |
dc.citation.epage | 91 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000502328900021 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |