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dc.contributor.authorWang, X. Shawnen_US
dc.contributor.authorChan, Chi-Hangen_US
dc.contributor.authorDu, Jieqiongen_US
dc.contributor.authorWong, Chien-Hengen_US
dc.contributor.authorLi, Yileien_US
dc.contributor.authorDu, Yuanen_US
dc.contributor.authorKuan, Yen-Chengen_US
dc.contributor.authorHu, Boyuen_US
dc.contributor.authorChang, Mau-Chung Franken_US
dc.date.accessioned2020-01-02T00:03:29Z-
dc.date.available2020-01-02T00:03:29Z-
dc.date.issued2018-01-01en_US
dc.identifier.isbn978-1-5386-4545-1en_US
dc.identifier.issn1529-2517en_US
dc.identifier.urihttp://hdl.handle.net/11536/153335-
dc.description.abstractThis paper presents an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. A two-level 2x8 master-slave hierarchical interleaved architecture is employed. A complementary dual-loop-assisted buffer is proposed to achieve both high linearity and bandwidth with low power. This time-interleaved ADC achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers.en_US
dc.language.isoen_USen_US
dc.titleAn 8.8-GS/s 8b Time-Interleaved SAR ADC with 50-dB SFDR Using Complementary Dual-Loop-Assisted Buffers in 28nm CMOSen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2018 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC)en_US
dc.citation.spage88en_US
dc.citation.epage91en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000502328900021en_US
dc.citation.woscount0en_US
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