High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning

Abstract

We present the first demonstration of 1T4R Resistive RAM (RRAM) array storing two bits per RRAM cell. Our HfO2-based RRAM is built using a logic foundry technology that is fully compatible with the CMOS back-end process. We present a new approach to program RRAM cells using gradual SET/RESET pulses while minimizing disturbances on adjacent cells (belonging to the same 1T4R RRAM structure) this new approach makes pour multiple-bits-per-cell 1T4R RRAM array demonstration possible. We report over 106 cycles of endurance and a projected 10-year retention at 120 degrees C. Using measured data from our 2 bits-per-cell 1T4R RRAM array, we analyze multiple deep learning applications and demonstrate high degrees of inference accuracy (within 0.01% of ideal values).