標題: First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications
作者: Chang, S. -W.
Sung, P. -J.
Chu, T-Y.
Lu, D. D.
Wang, C. -J.
Lin, N. -C.
Su, C. -J.
Lo, S. -H.
Huang, H. -F.
Li, J. -H.
Huang, M. -K.
Huang, Y. -C.
Huang, S. -T.
Wang, H. -C.
Huang, Y. -J.
Wang, J. -Y.
Yu, L. -W
Huang, Y. -F.
Hsueh, F. -K.
Wu, C. -T.
Ma, W. C. -Y.
Kao, K. -H.
Lee, Y. -J.
Lin, C. -L.
Chuang, R. W.
Huang, K. -P.
Samukawa, S.
Li, Y.
Lee, W. -H.
Chao, T. -S.
Huang, G. -W.
Wu, W. -F.
Li, J. -Y.
Shieh, J. -M.
Yeh, W. -K.
Wang, Y. -H.
電子物理學系
電機工程學系
Department of Electrophysics
Department of Electrical and Computer Engineering
公開日期: 1-Jan-2019
摘要: For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.
URI: http://hdl.handle.net/11536/155250
ISBN: 978-1-7281-4031-5
ISSN: 2380-9248
期刊: 2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
起始頁: 0
結束頁: 0
Appears in Collections:Conferences Paper