Reliability issues for high performance nanoscale CMOS technologies with channel mobility enhancing schemes

Abstract

In this talk, an overview of the mobility enhancing techniques for high performance/low power CMOS technologies will be introduced first. Two categories for mobility enhancing schemes, channel induced strain using Si/SiGe, and hybrid-substrate engineering, with (100) and (110) orientations, will be discussed next. In terms of the device reliability, different mechanisms are responsible for these two different technologies. While we have paid much more attention on the performance of these technologies, the device reliability has not been taken care of in the past studies. As a consequence, this talk will address several examples of these mobility enhancing schemes and their impact on the device reliability for advanced CMOS technologies for 65 nm and beyond.