標題: An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications
作者: Chen, PL
Chung, CC
Lee, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2005
摘要: An all-digital phase locked loop (ADPLL) with cascaded dynamic phase average (DPA) loop for wide multiplication range applications is presented in this paper. The multiplication factor can range from 4 to 65025 (255 x 255). The proposed architecture involves a minimum of hardware and improves jitter performance to reduce the noise and jitter associated with input reference. The dynamic phase averaging (DPA) loop control employing digital phase estimators (DPE) enhances frequency detection resolution and loop stability. A (Q.R) vector counter and an additional state counter serve as phase estimators. The proposed ADPLL includes cascaded DPA loops: the first stage is low frequency loop and the second stage is high frequency loop. A proto-type chip has been implemented with 0.18 mu m 1P6M CMOS process that can operate from 2MHz to 500MHz. The input frequency ranges from 5KHz to 50MHz. Thus it not only reduces the cost and design complexity of ADPLL, but also offers particular advantages for wide multiplication range applications.
URI: http://hdl.handle.net/11536/17790
ISBN: 0-7803-8834-8
ISSN: 0271-4302
期刊: 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS
起始頁: 4875
結束頁: 4878
顯示於類別:會議論文