標題: A low-complexity B-spline based digital sample rate conversion circuit architecture
作者: Lin, CC
Chi, HF
電信工程研究所
Institute of Communications Engineering
公開日期: 2005
摘要: This paper presents a low-complexity digital sample rate conversion (SRC) circuit architecture with arbitrary factor conversion ratio. The strategy in deciding SRC system parameters is given to guarantee that both the anti-imaging and the anti-aliasing requirements can be satisfied. The significant reduction in the complexity of the proposed structure allows simple VLSI implementation without affecting the performance. A parallel cascaded integrator comb (CIC) filter circuit without high intermediate sample rate and a multiplier-less linear interpolator are also developed to obtain a cost-effective and high-speed SRC circuit.
URI: http://hdl.handle.net/11536/17939
ISBN: 0-7803-9029-6
期刊: ISSCS 2005: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, Proceedings
起始頁: 505
結束頁: 508
Appears in Collections:Conferences Paper