標題: A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end
作者: Chen, WZ
Cheng, YL
Lin, DS
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2004
摘要: A fully integrated 10 Gbps optical receiver analog front-end, includes a trans-impedance amplifier (TIA) and a limiting amplifier (LA), is fabricated using a 0.18 mum CMOS technology. The receiver front-end provides a conversion gain up to 85 dBOmega and -3 dB bandwidth of 7.6 GHz. The sensitivity of the optical receiver is - 13 dBm at a bit-error rate of 10(-12) with 2(31)-1 pseudo-random bits. 3-D symmetric transformers are utilized in the AFE design for bandwidth enhancement.
URI: http://hdl.handle.net/11536/18102
ISBN: 0-7803-8480-6
期刊: ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE
起始頁: 263
結束頁: 266
Appears in Collections:Conferences Paper