A parallel multi-pattern PRBS generator and BER tester for 40(+) Gbps Serdes applications

Abstract

This paper presents the design of a programmable PRBS generator and a BER tester according to CCITT recommendations. Implemented in a parallel feedback configuration, this IC features PRBS generation of the sequences of length 2(7)-1, 2(10)-1, 2(15)-1, 2(23)-1,and 2(31)-l b for up to 40+Gbps serdes applications with 1:16 multiplexing and demultpilexing. The mark densities of 1/2, 1/4 and 1/8 for each of the patterns are also selectable. This IC could be used as a low cost substitute for more expensive bit error rate test system. Implemented in a 0.18 mum CMOS process, the total power dissipation is 141mW.