標題: A low power and high speed viterbi decoder chip for WLAN applications
作者: Lin, CC
Wu, CC
Lee, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2003
摘要: This paper presents a 166Mb/s, 64-state, radix-4, 16-level soft decison Viterbi decoder for high speed WLAN applications. With the path merging and trace forward techniques, the memory read operations are reduced to save power cunsumption. A test chip is fabricated in 0.35 mum 1P4M CMOS process, and can achieve the maximum throughout rate of 166Mbit/s under 3.3V The measured power consumption is below 55mW under 66M6/s throughput rate at 2.2V.
URI: http://hdl.handle.net/11536/18596
ISBN: 0-7803-7995-0
期刊: ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE
起始頁: 723
結束頁: 726
Appears in Collections:Conferences Paper