MOS-bounded diodes for on-chip ESD protection in a 0.15-mu m shallow-trench-isolation salicided CMOS process

Abstract

Novel diode structures without the shallow trench isolation (STI) across the p/n junction for ESD protection in a 0.15-mum CMOS process are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the STI isolation across the p/n junction in the diode structure. Without the STI boundary across the p/n junction of diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can provide more effective protection to the internal circuits, as compared to the other diode structures under reverse-biased condition. Such PMOS-bounded and NMOS-bounded dodes are fully process-compatible to general CMOS processes without additional process modification or mask layers.