標題: A 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applications
作者: Wu, CY
Chou, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2003
摘要: A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0.18um CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.
URI: http://hdl.handle.net/11536/18718
ISBN: 4-89114-034-8
期刊: 2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS
起始頁: 149
結束頁: 152
Appears in Collections:Conferences Paper