完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | KER, MD | en_US |
dc.contributor.author | WU, CY | en_US |
dc.date.accessioned | 2014-12-08T15:03:20Z | - |
dc.date.available | 2014-12-08T15:03:20Z | - |
dc.date.issued | 1995-06-01 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/1872 | - |
dc.description.abstract | The positive-feedback regenerative process in a p-n-p-n structure during CMOS latchup transition has been modeled by a time-varying positive transient pole, The maximum peak value of the positive pole and the time required to first initiate the positive pole are adopted as two useful and meaningful parameters to quantitatively investigate the influence of device parameters on the positive-feedback regeneration of CMOS latchup. Some design guidelines can be obtained to improve latchup immunity of CMOS IC's. | en_US |
dc.language.iso | en_US | en_US |
dc.title | MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .2. QUANTITATIVE-EVALUATION | en_US |
dc.type | Article | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 42 | en_US |
dc.citation.issue | 6 | en_US |
dc.citation.spage | 1149 | en_US |
dc.citation.epage | 1155 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1995QZ20000019 | - |
dc.citation.woscount | 8 | - |
顯示於類別: | 期刊論文 |