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dc.contributor.authorKER, MDen_US
dc.contributor.authorWU, CYen_US
dc.date.accessioned2014-12-08T15:03:20Z-
dc.date.available2014-12-08T15:03:20Z-
dc.date.issued1995-06-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://hdl.handle.net/11536/1872-
dc.description.abstractThe positive-feedback regenerative process in a p-n-p-n structure during CMOS latchup transition has been modeled by a time-varying positive transient pole, The maximum peak value of the positive pole and the time required to first initiate the positive pole are adopted as two useful and meaningful parameters to quantitatively investigate the influence of device parameters on the positive-feedback regeneration of CMOS latchup. Some design guidelines can be obtained to improve latchup immunity of CMOS IC's.en_US
dc.language.isoen_USen_US
dc.titleMODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .2. QUANTITATIVE-EVALUATIONen_US
dc.typeArticleen_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume42en_US
dc.citation.issue6en_US
dc.citation.spage1149en_US
dc.citation.epage1155en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1995QZ20000019-
dc.citation.woscount8-
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