標題: Negative substrate bias enhanced breakdown hardness in ultra-thin oxide pMOSFETs
作者: Wang, TH
Tsai, CW
Chen, MC
Chan, CT
Chiang, HK
Lu, SH
Hu, HC
Chen, TF
Yang, CK
Lee, MT
Wu, DY
Chen, JK
Chien, SC
Sun, SW
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2003
摘要: Negative substrate bias enhanced breakdown hardness in ultra-thin oxide (1.4nm) pMOS is observed. This result is believed due to the increase of hole stress current during breakdown progression via breakdown induced carrier heating. Numerical analysis of substrate bias effect on hole tunneling current is performed to support the proposed theory. This phenomenon is particularly significant to gate oxide reliability in floating substrate (PD-SOI) or forward-biased substrate devices.
URI: http://hdl.handle.net/11536/18730
ISBN: 0-7803-7649-8
期刊: 41ST ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM
起始頁: 437
結束頁: 441
Appears in Collections:Conferences Paper