標題: ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout consideration
作者: Ker, MD
Chuang, CH
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2001
URI: http://hdl.handle.net/11536/19014
ISBN: 0-7803-6675-1
期刊: PROCEEDINGS OF THE 2001 8TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS
起始頁: 85
結束頁: 90
Appears in Collections:Conferences Paper