| 標題: | Novel diode structures and ESD protection circuits in a 1.8-V 0.15-mu m partially-depleted SOI salicided CMOS process |
| 作者: | Ker, MD Hung, KK Tang, HTH Huang, SC Chen, SS Wang, MC 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| 公開日期: | 2001 |
| URI: | http://hdl.handle.net/11536/19016 |
| ISBN: | 0-7803-6675-1 |
| 期刊: | PROCEEDINGS OF THE 2001 8TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS |
| 起始頁: | 91 |
| 結束頁: | 96 |
| Appears in Collections: | Conferences Paper |
- Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technology / Ker, MD;Hong, KK;Chen, TY;Tang, H;Huang, SC
- 絕緣層上有矽互補式金氧半製程技術 / 洪根剛;Kei-Kang Hung;柯明道;Ming-Dou Ker
- Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process / Ker, MD;Chen, TY
- ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology / Ker, MD;Chuang, CH;Lo, WY
- Substrate-triggered ESD protection circuit without extra process modification / Ker, MD;Chen, TY
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