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dc.contributor.authorKer, MDen_US
dc.contributor.authorJiang, HCen_US
dc.contributor.authorPeng, JJen_US
dc.contributor.authorShieh, TLen_US
dc.date.accessioned2014-12-08T15:26:50Z-
dc.date.available2014-12-08T15:26:50Z-
dc.date.issued2001en_US
dc.identifier.isbn0-7803-7057-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/19091-
dc.description.abstractA program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "Guard Ring Automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.en_US
dc.language.isoen_USen_US
dc.titleAutomatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC'sen_US
dc.typeProceedings Paperen_US
dc.identifier.journalICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGSen_US
dc.citation.spage113en_US
dc.citation.epage116en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000176019100028-
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