標題: Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS process
作者: Ker, MD
Lo, WY
Chen, TY
Tang, H
Chen, SS
Wang, MC
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2001
摘要: An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-mum shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.
URI: http://hdl.handle.net/11536/19101
ISBN: 0-7695-1026-4
期刊: INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS
起始頁: 267
結束頁: 272
Appears in Collections:Conferences Paper