標題: | ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design |
作者: | Chen, TY Ker, MD 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2001 |
摘要: | The operation principles of gate-driven design and substrate-triggered design for ESD (ElectroStatic Discharge) protection are first explained by energy-band diagrams in this paper. The on-chip ESD protection devices realized in 0.18-mum and 0.35-mum CMOS processes are used to verify the efficiency of gate-driven or substrate-triggered designs. The substrate-triggered design can effectively and continually improve ESD robustness of protection devices than the gate-driven design. The HEM (Human-Body-Model) ESD level of NMOS with a W/L of 300 mum/0.3 mum can be improved from the original 0.8kV to become 3.3kV by the substrate-triggered design. But, the gate-driven design cannot continually improve the ESD level of the same device in the subquarter-micron CMOS process. |
URI: | http://hdl.handle.net/11536/19157 |
ISBN: | 0-7803-6412-0 |
期刊: | 2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS |
起始頁: | 232 |
結束頁: | 235 |
顯示於類別: | 會議論文 |