標題: A methodology for fault model development for hierarchical linear systems
作者: Huang, YC
Lee, CL
Lin, JW
Chen, JE
Su, CC
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2000
摘要: In this paper, a methodology to develop fault models for hierarchical linear systems which are composed of operational amplifiers(OP) is demonstrated and presented. The methodology, at first, presents a transfer function model for the open-loop OP based on analysis of element faults at the transistor level. Then it derives a transfer function model for the closed loop OP based on the derived open-loop OP level model, again a higher level fault model for a module which is composed of closed loop OPs. The models can handle ac faults. The benchmark state-variable filter is used as an example to demonstrate for this methodology. an application of the derived models to Monte-Carlo simulation to save computation time is also demonstrated.
URI: http://hdl.handle.net/11536/19234
ISBN: 0-7695-0888-X
期刊: PROCEEDINGS OF THE NINTH ASIAN TEST SYMPOSIUM (ATS 2000)
起始頁: 90
結束頁: 95
Appears in Collections:Conferences Paper