標題: | Power driven partial scan |
作者: | Jou, JY Nien, MC 交大名義發表 電子工程學系及電子研究所 National Chiao Tung University Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1997 |
摘要: | The power consumption and testability are two of major considerations in modem VLSI design, A full-scan method had been used widely in the past to improve the testability of sequential circuits. Due to the lower overheads incurred the partial-scan design has gradually become popular. In this paper we propose a partial scan selection strategy that bases on the structural analysis approach and considers the area and power overheads simultaneously. A powerful sample-and-search algorithm is used to find the solution that minimizes the user-specified cost function in term of power and area overheads. The experimental results show that our sample-and-search algorithm can effectively find the best solution of the specified cost function for almost all circuits, and the saving of overheads an average for each specific cost function is significant. |
URI: | http://hdl.handle.net/11536/19705 |
ISBN: | 0-8186-8207-8 |
ISSN: | 1063-6404 |
期刊: | INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS |
起始頁: | 642 |
結束頁: | 647 |
顯示於類別: | 會議論文 |