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dc.contributor.authorChen, AYen_US
dc.contributor.authorWu, CYen_US
dc.contributor.authorWen, KAen_US
dc.date.accessioned2014-12-08T15:27:39Z-
dc.date.available2014-12-08T15:27:39Z-
dc.date.issued1996en_US
dc.identifier.isbn0-7803-3692-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/19917-
dc.description.abstractThe Viterbi algorithm is widely applied for communication to derive the maximun-likehood sequence estimates of transmitted data on channels with intersymbol interference (ISI) and/or coding. In this paper, we provide a VLSI design of Viterbi decoder for IS-54. Design features includes: switchable (2,1,5),(4,1,5) coder design, data inter-leaving, soft - decision. For hardware constrain, area efficiency is of great concern in handset design. Hence, optimized area efficient design is imple-mented.en_US
dc.language.isoen_USen_US
dc.titleDual-mode Viterbi decoder design for cellular mobileen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPIMRC'96 - THE SEVENTH IEEE INTERNATIONAL SYMPOSIUM ON PERSONAL, INDOOR AND MOBILE RADIO COMMUNICATIONS, PROCEEDINGS, VOLS 1-3en_US
dc.citation.spage1029en_US
dc.citation.epage1033en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1996BH25X00213-
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