| 標題: | Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture |
| 作者: | Huang, JD Joy, JY Shen, WZ 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| 公開日期: | 1995 |
| URI: | http://hdl.handle.net/11536/20017 |
| ISBN: | 0-8186-7213-7 |
| 期刊: | 1995 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN |
| 起始頁: | 359 |
| 結束頁: | 363 |
| 顯示於類別： | 會議論文 |
- 用戶可規劃閘陣列之邏輯合成與分割 / 黃俊達;Huang, Juinn-Dar;沈文仁, 周景揚;Wen-Zen Shen, Jing-Yang Jou
- Unified functional decomposition via encoding for FPGA technology mapping / Jiang, JH;Jou, JY;Huang, JD
- ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping / Huang, JD;Jou, JY;Shen, WZ
- BDD based lambda set selection in Roth-Karp decomposition for LUT architecture / Jiang, JH;Jou, JY;Huang, JD;Wei, JS
- A variable partitioning algorithm of BDD for FPGA technology mapping / Jiang, JH;Jou, JY;Huang, JD;Wei, JS
- Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping / SHEN, WZ;HUANG, JD;CHAO, SM
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