Cumulative Differential Non linearity Testing of ADCs

Abstract

This paper proposes a cumulative DNL (CDNL) test methodology for the BIST of ADCs. It analyzes the histogram of the DNL of a predetermined k LSBs distance to determine the DNL and gain error. The advantage of this method over others is that the numbers of required code bins and required samples are significantly reduced. The simulation and measurements of a 12-bit ADC show that the proposed CDNL has an error of less than 5% with only 2(12) samples, which can only be achieved with 2(22) samples using the conventional method. It only needs 16 registers to store code bins in this experiment.