Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack

doi:10.1016/j.sse.2013.02.003

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DC 欄位	值	語言
dc.contributor.author	Cheng, C. H.	en_US
dc.contributor.author	Chou, K. I.	en_US
dc.contributor.author	Chin, Albert	en_US
dc.date.accessioned	2014-12-08T15:30:21Z	-
dc.date.available	2014-12-08T15:30:21Z	-
dc.date.issued	2013-04-01	en_US
dc.identifier.issn	0038-1101	en_US
dc.identifier.uri	http://dx.doi.org/10.1016/j.sse.2013.02.003	en_US
dc.identifier.uri	http://hdl.handle.net/11536/21700	-
dc.description.abstract	We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (V-t) of 0.31 V. This small EOT MOSFET was achieved by employing high-kappa CeO2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-kappa SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node. (C) 2013 Elsevier Ltd. All rights reserved.	en_US
dc.language.iso	en_US	en_US
dc.subject	Gate first	en_US
dc.subject	TiLaO	en_US
dc.subject	CeO2	en_US
dc.subject	Small EOT	en_US
dc.title	Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1016/j.sse.2013.02.003	en_US
dc.identifier.journal	SOLID-STATE ELECTRONICS	en_US
dc.citation.volume	82	en_US
dc.citation.issue		en_US
dc.citation.spage	111	en_US
dc.citation.epage	114	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000317701500021	-
dc.citation.woscount	2	-
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