標題: | Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack |
作者: | Cheng, C. H. Chou, K. I. Chin, A. 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | TiLaO;La2O3;Gate first;Low EOT |
公開日期: | 1-九月-2013 |
摘要: | We report a self-aligned and gate-first TiLaO/La2O3 n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (V-t) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process. (C) 2013 Elsevier B.V. All rights reserved. |
URI: | http://dx.doi.org/10.1016/j.mee.2013.03.082 http://hdl.handle.net/11536/22106 |
ISSN: | 0167-9317 |
DOI: | 10.1016/j.mee.2013.03.082 |
期刊: | MICROELECTRONIC ENGINEERING |
Volume: | 109 |
Issue: | |
起始頁: | 35 |
結束頁: | 38 |
顯示於類別: | 期刊論文 |