標題: A 10Bit, 10MS/s, Low Power Cyclic ADC
作者: Chen, Chien-Hung
Chen, Wei-Zen
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Cyclic ADC;Residual Amplifier;Background Calibration
公開日期: 2013
摘要: A low power, small form factor, cyclic ADC is proposed. By replacing the MDAC with an open loop residual amplifier, it relaxes the gain bandwidth requirement of the operational amplifier to save power. The residual amplifier is background calibrated without extra replica to avoid performance mismatches, and also save area and power. Timing reschedule scheme is proposed for each conversion step to accelerate conversion speed. At 10 MS/s operation, the corresponding FOM is 0.45pJ/conv.-step. Fabricated in a 85nm CMOS technology, the chip size is 0.077mm(2).
URI: http://hdl.handle.net/11536/23933
ISBN: 978-1-4673-4743-3
期刊: 2013 INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT)
起始頁: 155
結束頁: 158
Appears in Collections:Conferences Paper