一個十位元,每秒一千萬次取樣低功率迴圈式類比數位轉換器

Abstract

操作在中速及中解析度之類比數位轉換器廣泛應用在可攜式電子產品中，其大約操作在每秒數十個百萬次的資料速度及8到10個位元解析度。在傳統倍乘數位類比轉換器架構中，運算放大器是最消耗功率的部分。本篇論文提出一個更節能的迴圈式類比數位轉換器的解決方案，每個轉換步驟3.5位元輸出加快轉換速度，以及在最後兩個處理週期使用時序重置技術以節省更多時間。此外背景校準電路無須額外的殘值放大器，可降低功率消耗和晶片面積。 本提出的迴圈式類比數位轉換器以85nm CMOS製程實作完成，晶片面積為0.96×0.715平方毫米。其可操作在每秒10個百萬次的資料速度及10位元解析度，量測結果顯示其微分和積分非線性誤差分別為+0.55/-0.82LSB和+1.6/-1.5LSB。類比電路操作在1.2伏特工作電壓，而數位電路操作在1伏特工作電壓，整體功率消耗約1.1毫瓦，其FOM值達0.45pJ/conv.-step。

ADCs which operate middle speed and medium resolution are widely applied in portable electronic devices. It is about several tens of MS/s and 8 to 10bit resolution. In conventional MDAC architecture, the operational amplifier is the largest consumer of power. The thesis presents a solution of the more power-efficient cyclic ADC. To speed up the conversion rate, there is 3.5bit conversion step, and the timing re-scheduled technique is utilized to save more time in the last two cycles. Besides, background calibration without extra residue amplifier to reduce power and chip area. The proposed cyclic ADC has been fabricated in a 85nm CMOS technology, the chip size is 0.96×0.715mm2. It can operate in 10MS/s and 10bit resolution. Experimental results reveal that the DNL and INL are +0.55/-0.82LSB and +1.6/-1.5LSB respectively at 10 MS/s. Analog circuits are operated under a 1.2V supply, and digital circuits are operated under a 1V supply. Total power dissipation is 1.1mW. The corresponding FOM (Figure of Merit) is 0.45pJ/conv.-step.