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dc.contributor.authorChen, Wei-Zenen_US
dc.contributor.authorLu, Tai-Youen_US
dc.contributor.authorWang, Yan-Tingen_US
dc.contributor.authorJian, Jhong-Tingen_US
dc.contributor.authorYang, Yi-Hungen_US
dc.contributor.authorChang, Kai-Tingen_US
dc.date.accessioned2014-12-08T15:36:22Z-
dc.date.available2014-12-08T15:36:22Z-
dc.date.issued2014-06-01en_US
dc.identifier.issn1549-8328en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2013.2295016en_US
dc.identifier.urihttp://hdl.handle.net/11536/24700-
dc.description.abstractA 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm(2). The PLL locking time is less than 3 mu s. This chip drains 24 mW from a 1.2 V power supply.en_US
dc.language.isoen_USen_US
dc.subjectHarmonic mixeren_US
dc.subjectPLLen_US
dc.subjectRSSIen_US
dc.subjecttripleren_US
dc.titleA 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisitionen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2013.2295016en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume61en_US
dc.citation.issue6en_US
dc.citation.spage1648en_US
dc.citation.epage1655en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000337152900005-
dc.citation.woscount0-
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