完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chiu, Yi-Wei | en_US |
dc.contributor.author | Hu, Yu-Hao | en_US |
dc.contributor.author | Tu, Ming-Hsien | en_US |
dc.contributor.author | Zhao, Jun-Kai | en_US |
dc.contributor.author | Chu, Yuan-Hua | en_US |
dc.contributor.author | Jou, Shyh-Jye | en_US |
dc.contributor.author | Chuang, Ching-Te | en_US |
dc.date.accessioned | 2014-12-08T15:36:49Z | - |
dc.date.available | 2014-12-08T15:36:49Z | - |
dc.date.issued | 2014-09-01 | en_US |
dc.identifier.issn | 1549-8328 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSI.2014.2332267 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/25204 | - |
dc.description.abstract | This paper presents a new bit-interleaving 12T sub-threshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical V-DD to 350 mV (similar to 100 mV lower than the threshold voltage) with V-DDMIN limited by Read operation. Data can be written successfully for V-DD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 mu W at 350 mV, 25 degrees C. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Data-aware | en_US |
dc.subject | low supply voltage | en_US |
dc.subject | SRAM | en_US |
dc.subject | subthreshold voltage | en_US |
dc.subject | write-assist | en_US |
dc.title | 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCSI.2014.2332267 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | en_US |
dc.citation.volume | 61 | en_US |
dc.citation.issue | 9 | en_US |
dc.citation.spage | 2578 | en_US |
dc.citation.epage | 2585 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000341593700007 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |