標題: Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode
作者: Zhu, SY
Yu, HY
Whang, SJ
Chen, JH
Shen, C
Zhu, CX
Lee, SJ
Li, MF
Chan, DSH
Yoo, WJ
Du, AY
Tung, CH
Singh, J
Chin, A
Kwong, DL
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: high-kappa;metal gate;MOSFET;Schottky
公開日期: 1-五月-2004
摘要: This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-kappa gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi source/drain (S/D), excellent electrical performance of I-on/I-off similar to 10(7) - 10(8) and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, I-on/I-off can reach similar to 10(5) at V-ds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-kappa dielectric and metal-gate materials to be used in the future generation CMOS technology.
URI: http://dx.doi.org/10.1109/LED.2004.826569
http://hdl.handle.net/11536/26815
ISSN: 0741-3106
DOI: 10.1109/LED.2004.826569
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 25
Issue: 5
起始頁: 268
結束頁: 270
顯示於類別:期刊論文


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